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ltc 6947 1 6947f for more information www.linear.com/ltc6947 typical a pplica t ion fea t ures descrip t ion ultralow noise 0.35ghz to 6ghz fractional-n synthesizer the lt c ? 6947 is a high performance, low noise , 6ghz phase-locked loop ( pll), including a reference divider, phase-frequency detector ( pfd), ultralow noise charge pump, fractional feedback divider, and vco output divider. the fractional divider uses an advanced , 4 th order ? modulator which provides exceptionally low spurious levels. this allows wide loop bandwidths, producing extremely low integrated phase noise values. the programmable vco output divider, with a range of 1 through 6, extends the output frequency range. the dif- ferential, low-noise output buffer has user-programmable output power ranging from C4.3dbm to +4.5 dbm, and may be muted through either a digital input pin or software. the ultralow noise charge pump contains selectable high and low voltage clamps useful for vco monitoring, and also may be set to provide a v + /2 bias. all device settings are controlled through a spi- compatible serial port. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and fracnwizard is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 11ghz source for satellite communications system phase noise, f rf = 11.260ghz a pplica t ions n low noise fractional-n pll n no ? modulator spurs n 18-bit fractional denominator n 350mhz to 6ghz vco input range n C226dbc/hz normalized in-band phase noise floor n C274dbc/hz normalized in-band 1/f noise n C157dbc/hz wideband output phase noise floor n excellent integer boundary spurious performance n output divider (1 to 6, 50% duty cycle) n output buffer muting n charge pump supply from 3.15v to 5.25v n charge pump current from 1ma to 11.2ma n reference input frequency up to 425mhz n fast frequency switching n fracnwizard? software design t ool support n wireless basestations ( lt e , wimax, w-cdma, pcs) n broadband wireless access n microwave data links n military and secure radio n test and measurement 47f 0.1f r = 2, f pfd = 50mhz n = 102 to 113 lbw = 33.6khz 3.3nf 0.01f 1f 0.01f 3.3v 3.3v 0.01f 68nh 68nh 4.99k 0.01f 5v 3.3v 60.4 auxiliary outputs f lo /2, /4, /6, /8, /10 or /12 vtune 5v 5v 100pf 100pf 10nf 3.3v f lo = 10.2ghz to 11.3ghz in 381.4hz steps ltc6947iufd stat vco ? cs mute sdi v d + ldo rf + rf ? gnd sclk vco + gnd v rf + ref + bb sdo gnd gnd gnd gnd gnd v vco + gnd v cp + cp v ref + ref ? gnd 75 0.1f 1nf 4.99k 100pf 0.1f 0.1f 0.1f 10nf 220nf 100pf 47nf 100mhz 51.1 1f 3.3v 1f ma-com maoc-009266 0.1f 13v 3.3v f lo /2 60.4 ? + lt1678is8 out 6947 ta01a spi bus + phase noise (dbc/hz) ?80 ?170 ?90 ?110 ?130 ?150 ?100 ?120 ?140 ?160 ?180 6946 ta01b offset frequency (hz) 100 1k 10k 10m 100m 1m100k rms noise = 0.549 rms jitter = 135fs f pfd = 50mhz loop bw = 34khz intn = 0 cple = 1
ltc 6947 2 6947f for more information www.linear.com/ltc6947 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltages v + (v ref + , v rf + , v vco + , v d + ) to gnd ................... 3 .6 v v cp + to gnd ......................................................... 5 .5 v voltage on cp pin ................. gn d C 0.3 v to v cp + + 0.3 v voltage on all other pins ........... gn d C 0.3 v to v + + 0.3 v operating junction temperature range , t j ltc 6947 i ( note 2) ............................. C 40 c to 105 c junction temperature , t jmax ................................ 125 c storage temperature range .................. C 65 c to 150 c (note 1) 9 10 top view 29 gnd ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 ref + stat cs sclk sdi sdo ldo v d + gnd gnd gnd gnd gnd gnd vco + vco ? ref ? v ref + cp v cp + gnd v vco + mute gnd rf ? rf + v rf + bb 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, jcbottom = 7c/w exposed pad (pin 29) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking package description junction temperature range ltc6947iufd#pbf ltc6947iufd#trpbf 6947 28-lead (4mm 5mm) plastic qfn C40c to 105c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics symbol parameter conditions min typ max units reference inputs (ref + , ref C ) f ref input frequency l 10 425 mhz v ref input signal level single-ended, 1f ac-coupling capacitors l 0.5 2 2.7 v p-p input slew rate l 20 v/s input duty cycle 50 % self-bias voltage l 1.65 1.85 2.25 v input resistance differential l 5.8 8.4 11.6 k input capacitance differential 14 pf the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v unless otherwise specified (note?2). all voltages are with respect to gnd.
ltc 6947 3 6947f for more information www.linear.com/ltc6947 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units vco input (vco + , vco C ) f vco input frequency l 350 6000 mhz p vcoi input power level r z = 50, single-ended l C8 0 6 dbm input resistance single-ended, each input l 94 132 161 rf output (rf + , rf C ) f rf output frequency l 350 6000 mhz o output divider range all integers included l 1 6 output duty cycle 50 % output resistance single-ended, each output to v rf + l 100 136 175 p rf-se output power, single-ended, f rf = 900mhz rfo[1:0] = 0, r z = 50, lc match rfo[1:0] = 1, r z = 50, lc match rfo[1:0] = 2, r z = 50, lc match rfo[1:0] = 3, r z = 50, lc match l l l l C9 C6.1 C2.9 0.1 C7.3 C4.5 C1.4 1.5 C5.5 C2.8 0.2 3.0 dbm dbm dbm dbm output power, muted, f rf = 900mhz r z = 50, single-ended, o = 2 to 6 l C80 dbm mute enable time l 110 ns mute disable time l 170 ns phase/frequency detector f pfd input frequency integer mode fractional mode ldoen = 0 ldov = 3, ldoen = 1 ldov = 2, ldoen = 1 ldov = 1, ldoen = 1 ldov = 0, ldoen = 1 l l l l l l 100 76.1 66.3 56.1 45.9 34.3 mhz mhz mhz mhz mhz mhz charge pump i cp output current range 8 settings (see table 6) 1 11.2 ma output current source/sink accuracy all settings, v(cp) = v cp + /2 6 % output current source/sink matching i cp = 1.0ma to 2.8ma, v(cp) = v cp + /2 i cp = 4.0ma to 11.2ma, v(cp) = v cp + /2 3.5 2 % % output current vs output voltage sensitivity (note 3) l 0.2 1.0 %/v output current vs temperature v(cp) = v cp + /2 l 170 ppm/c output hi-z leakage current i cp = 11.2ma, cpclo = cpchi = 0 (note 3) 0.03 na v clmp-lo low clamp voltage cpclo = 1 0.84 v v clmp-hi high clamp voltage cpchi = 1, referred to v cp + C0.96 v v mid mid-supply output bias ratio referred to (v cp + C gnd) 0.48 v/v reference (r) divider r divide range all integers included l 1 31 counts vco (n) divider n divide range all integers included, integer mode all integers included, fractional mode l l 32 35 1023 1019 counts counts fractional ? modulator numerator range all integers included l 1 262143 counts the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v unless otherwise specified (note?2). all voltages are with respect to gnd.
ltc 6947 4 6947f for more information www.linear.com/ltc6947 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units modulator ldo output voltage ldo enabled, four values ldo disabled 1.7 to 2.6 v d + v v external pin capacitance required for ldo stability l 0.047 0.1 1 f digital pin specifications v ih high level input voltage mute, cs, sdi, sclk l 1.55 v v il low level input voltage mute, cs, sdi, sclk l 0.8 v v ihys input voltage hysteresis mute, cs, sdi, sclk 250 mv input current mute, cs, sdi, sclk l 1 a i oh high level output current sdo and stat , v oh = v d + C 400mv l C3.3 C1.9 ma i ol low level output current sdo and stat , v ol = 400mv l 2.0 3.4 ma sdo hi-z current l 1 a digital timing specifications (see figure 7 and figure 8) t ckh sclk high time l 25 ns t ckl sclk low time l 25 ns t css cs setup time l 10 ns t csh cs high time l 10 ns t cs sdi to sclk setup time l 6 ns t ch sdi to sclk hold time l 6 ns t do sclk to sdo time to v ih /v il /hi-z with 30pf load l 16 ns power supply voltages v ref + supply range l 3.15 3.3 3.45 v v d + supply range l 3.15 3.3 3.45 v v rf + supply range l 3.15 3.3 3.45 v v vco + supply range l 3.15 3.3 3.45 v v cp + supply range l 3.15 5.25 v power supply currents i dd v d + supply current digital inputs at supply levels, pdfn = 1 digital inputs at supply levels, fractional mode, f pfd = 66.3mhz mhz, ldov[1:0] = 3 l l 18.2 1500 22 a ma i cc(5v) sum v cp + supply currents i cp = 11.2ma i cp = 1.0ma pdall = 1 l l l 34 12 230 40 14 650 ma ma a i cc(3.3v) sum v ref + , v rf + , v vco + supply currents rf muted, od[2:0] = 1 rf enabled, rfo[1:0] = 0, od[2:0] = 1 rf enabled, rfo[1:0] = 3, od[2:0] = 1 rf enabled, rfo[1:0] = 3, od[2:0] = 2 rf enabled, rfo[1:0] = 3, od[2:0] = 3 rf enabled, rfo[1:0] = 3, od[2:0] = 4 to 6 pdall = 1 l l l l l l l 70.4 81.1 91.3 109.2 114.8 119.6 53 80 95 105 125 135 140 250 ma ma ma ma ma ma a the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v unless otherwise specified (note?2). all voltages are with respect to gnd.
ltc 6947 5 6947f for more information www.linear.com/ltc6947 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc6947i is guaranteed to meet specified performance limits over the full operating junction temperature range of C40c to 105c. note 3: for 0.9v < v(cp) < (v cp + C 0.9v). note 4: vco is crystek cvco55c-2328-2536. note 5: f vco = 6ghz, f offset = 40mhz. note 6: measured inside the loop bandwidth with the loop locked. note 7: reference frequency supplied by wenzel 501-04516, f ref = 100mhz, p ref = 10dbm. note 8: reference frequency supplied by wenzel 500-23571, f ref = 61.44mhz, p ref = 10dbm. note 9: output phase noise floor is calculated from normalized phase noise floor by l out = l norm + 10log 10 (f pfd ) + 20log 10 (f rf /f pfd ). note 10: output 1/f noise is calculated from normalized 1/f phase noise by l out(1/f) = l 1/f + 20log 10 (f rf ) C 10log 10 (f offset ). note 11: i cp = 5.6ma, f pfd = 50mhz, filt[1:0] = 0, loop bw = 31khz; f rf = 2415mhz, f vco = 2415mhz. note 12: measured using dc1846. note 13: vco is rfmd umx-918-d16-g. symbol parameter conditions min typ max units phase noise and spurious l min output phase noise floor (note 5) rfo[1:0] = 3, od[2:0] = 1, f rf = 6ghz C155 dbc/hz rfo[1:0] = 3, od[2:0] = 2, f rf = 3ghz C155 dbc/hz rfo[1:0] = 3, od[2:0] = 3, f rf = 2ghz C156 dbc/hz rfo[1:0] = 3, od[2:0] = 4, f rf = 1.5ghz C156 dbc/hz rfo[1:0] = 3, od[2:0] = 5, f rf = 1.2ghz C157 dbc/hz rfo[1:0] = 3, od[2:0] = 6, f rf = 1.0ghz C158 dbc/hz l norm( int) integer normalized in-band phase noise floor intn = 1, i cp = 5.6ma (notes 6, 7, 9) C226 dbc/hz l norm( frac) fractional normalized in-band phase noise floor intn = 0, cple = 1, i cp = 5.6ma (notes 6, 7, 9) C225 dbc/hz l 1/f normalized in-band 1/f phase noise i cp = 11.2ma (notes 6, 10) C274 dbc/hz in-band phase noise floor fractional mode, cple = 1 (notes 4, 6, 7, 10, 11) C109 dbc/hz integrated phase noise from 100hz to 40mhz fractional mode, cple = 1 (notes 4, 7, 11) 0.076 rms spurious fractional mode, f offset = f pfd , pll locked (notes 4, 7, 11, 12) C97 dbc the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v unless otherwise specified (note?2). all voltages are with respect to gnd.
ltc 6947 6 6947f for more information www.linear.com/ltc6947 t a = 25c. v ref + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v, intn = 0, dithen = 1, cple = 1, rfo[1:0] = 3, unless otherwise noted. typical p er f or m ance c harac t eris t ics charge pump sink current error vs voltage, temperature ref input sensitivity vs frequency rf output power vs frequency (single-ended on rf C ) charge pump source current error vs voltage, output current cp hi-z current vs voltage, temperature rf output hd2 vs output divide (single-ended on rf C ) charge pump source current error vs voltage, temperature charge pump sink current error vs voltage, output current rf output hd3 vs output divide (single-ended on rf C ) frequency (mhz) 0 sensitivity (dbm) ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?50 400 6947 g01 100 200 300 450 350 50 150 250 bst = 1 filt = 0 105c 25c ?40c output voltage (v) 0 current (na) 5 4 3 2 1 0 ?1 ?2 ?3 ?5 ?4 4.0 6947 g02 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 i cp = 11.2ma cprst = 1 cple = 0 105c 25c ?40c output voltage (v) 0 error (%) 5 4 3 2 1 0 ?1 ?2 ?3 ?5 ?4 4.0 6947 g03 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 cple = 0 1ma 5.6ma 11.2ma output voltage (v) 0 error (%) 5 4 3 2 1 0 ?1 ?2 ?3 ?5 ?4 4.0 6947 g04 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 i cp = 11.2ma cple = 0 105c 25c ?40c frequency (ghz) 0.25 p out (dbm) 0.5 1.0 2.0 1.5 1.25 3.25 4.25 6947 g07 ?0.5 ?1.5 0 ?2.5 ?1.0 ?2.0 2.25 5.25 6.25 105c 25c ?40c l c = 68nh c s = 100pf f vco (ghz) ?60 hd2 (dbc) ?55 ?50 ?45 ?40 ?35 ?30 6947 g08 ?25 ?20 l c = 68nh, c s = 100pf f rf = f vco /o o = 3 o = 2 o = 1 o = 6 o = 4 o = 5 0.25 1.25 3.25 4.25 2.25 5.25 6.25 0.25 1.25 3.25 4.25 2.25 5.25 6.25 f vco (ghz) ?35 hd3 (dbc) ?30 ?25 ?20 6947 g09 ?15 ?10 ?5 l c = 68nh c s = 100pf f rf = f vco /o o = 6 o = 3 o = 2 o = 1 o = 5 o = 4 output voltage (v) 0 error (%) 5 4 3 2 1 0 ?1 ?2 ?3 ?5 ?4 4.0 6947 g06 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 i cp = 11.2ma cple = 0 105c 25c ?40c output voltage (v) 0 error (%) 5 4 3 2 1 0 ?1 ?2 ?3 ?5 ?4 4.0 6947 g05 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 cple = 0 1ma 5.6ma 11.2ma
ltc 6947 7 6947f for more information www.linear.com/ltc6947 t a = 25c. v ref + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v, intn = 0, dithen = 1, cple = 1, rfo[1:0] = 3, unless otherwise noted. typical p er f or m ance c harac t eris t ics normalized in-band phase noise floor vs cp current mute output power vs f vco and output divide ( single-ended on rf C ) closed-loop phase noise f rf = 2415mhz vco input sensitivity vs frequency closed-loop phase noise f rf = 3330mhz normalized in-band phase noise floor vs f vco spurious response f rf = 2415mhz, f ref = 100mhz, f pfd = 50mhz, loop bw = 31khz spurious response f rf = 3330mhz, f ref = 61.44mhz, f pfd = 61.44 mhz, loop bw = 14.5khz supply current vs temperature f vco (mhz) p out at f vco /o (dbm) ?70 ?60 ?50 6947 g10 ?80 ?90 ?100 ?110 ?30 ?40 l c = 68nh, c s = 100pf, p vco = 0dbm, f rf = f vco /o o = 1 o = 4 o = 6 o = 2 o = 3 0.25 1.25 3.25 4.25 2.25 5.25 6.25 o = 5 frequency (ghz) sensitivity (dbm) ?30 ?25 ?20 6947 g11 ?35 ?10 ?15 0.25 1.25 3.25 4.25 2.25 5.25 6.25 105c 25c ?40c f vco (ghz) 1 ?227 phase noise floor (dbc/hz) ?226 ?224 2 3 6947 g12 4 ?222 ?220 ?225 ?223 ?221 5 6 i cp = 5.6ma cple = 1 fractional-n integer-n i cp (ma) 1 ?227 phase noise floor (dbc/hz) ?226 3 5 6947 g13 7 ?224 ?222 ?225 ?223 9 11 f vco = 5ghz cple = 1 fractional-n integer-n frequency offset (mhz in 10khz segments) ?200 ?91dbc ?150 ?140 p out (dbm) ?120 ?100 ?80 50 100 150 0 6947 g16 ?100 ?50 0 200 ?60 ?40 ?20 rbw = 10hz vbw = 10hz intn = 0 cple = 1 o = 1 vco = note 4 notes 7, 11 ?88dbc frequency offset (mhz in 10khz segments) ?246 ?90dbc ?184 ?140 p out (dbm) ?120 ?100 ?80 61.4 123 184 0 6947 g17 ?123?61.4 0 246 ?60 ?40 ?20 rbw = 10hz vbw = 10hz intn = 0 cple = 1 o = 1 vco = note 13 note 8 ?89dbc t j (c) ?40 83 3.3v current (ma) 5v current (ma) 84 86 ?20 0 20 40 6947 g18 60 88 90 85 87 89 19 21 23 25 26 20 22 24 80 100 o = 1, mute = 0 rfo = 3, i cp = 5.6ma excludes v d + offset frequency (hz) ?140 phase noise (dbc/hz) ?130 ?110 ?90 100 10k 100k 10m 40m 6947 g14 ?150 1k 1m ?100 ?120 ?170 ?160 rms noise = 0.076 rms jitter = 87fs f pfd = 50mhz loop bw = 31khz vco = note 4 intn = 0 cple = 1 note 11 offset frequency (hz) ?140 phase noise (dbc/hz) ?130 ?110 ?90 100 10k 100k 10m 40m 6947 g15 ?150 1k 1m ?100 ?120 ?170 ?160 rms noise = 0.074 rms jitter = 62fs f pfd = 61.44mhz loop bw = 14.5khz vco = note 13 intn = 0 cple = 1
ltc 6947 8 6947f for more information www.linear.com/ltc6947 t a = 25c. v ref + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v, intn = 0, dithen = 1, cple = 1, rfo[1:0] = 3, unless otherwise noted. typical p er f or m ance c harac t eris t ics v d + supply current vs ldov, f pfd (intn = 0, pdfn = 0) v d + supply current vs ldov, temperature (intn = 0, pdfn = 0, f pfd noted) p in func t ions ref + , ref C (pins 1, 28): reference input signals. this differential input is buffered with a low noise amplifier, which feeds the reference divider. they are self-biased and must be ac-coupled with 1 f capacitors. if used single- ended with v ref + 2.7v p-p , bypass ref C to gnd with a 1f capacitor. if used single-ended with v ref + > 2.7v p-p , bypass ref C to gnd with a 47pf capacitor. s tat (pin 2): status output. this signal is a configurable logical or combination of the unlok, lok, thi, and tlo status bits, programmable via the status register. see the operation section for more details. cs (pin 3): serial port chip select. this cmos input initi- ates a serial port communication burst when driven low, ending the burst when driven back high. see the operation section for more details. sclk (pin 4): serial port clock. this cmos input clocks serial port input data on its rising edge. see the operation section for more details. sdi (pin 5): serial port data input. the serial port uses this cmos input for data. see the operation section for more details. sdo (pin 6): serial port data output. this cmos three- state output presents data from the serial port during a read communication burst. optionally attach a resistor of >200k to gnd to prevent a floating output. see the ap- plications information section for more details. ldo (pin 7): ? modulator ldo bypass pin. this pin should be bypassed directly to the ground plane using a low esr (<0.8) 0.1 f ceramic capacitor as close to the pin as possible. v d + (pin 8): 3.15 v to 3.45 v positive supply pin for serial port and ? modulator circuitry. this pin should be by- passed directly to the ground plane using a 0.1 f ceramic capacitor as close to the pin as possible. mute (pin 9): rf mute. the cmos active-low input mutes the rf differential outputs while maintaining internal bias levels for quick response to de-assertion. f pfd (mhz) 5 15 0 2 4 6 8 supply current (ma) 10 12 14 16 20 25 35 45 55 6947 g19 65 75 18 ldoen = 0 ldov = 3 ldov = 2 ldov = 1 ldov = 0 t j (c) ?40 ?20 4 6 8 supply current (ma) 10 12 14 16 20 0 20 40 60 6947 g20 80 100 18 ldoen = 0, 75mhz ldov = 3, 65mhz ldov = 2, 55mhz ldov = 1, 45mhz ldov = 0, 30mhz
ltc 6947 9 6947f for more information www.linear.com/ltc6947 p in func t ions gnd (pins 10, 17, 18, 19, 20, 21, 22, exposed pad pin 29): negative power supply ( ground). these pins should be tied directly to the ground plane with multiple vias for each pin. the package exposed pad must be soldered directly to the pcb land. the pcb land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance. rf C , rf + (pins 11, 12): rf output signals. the vco output divider is buffered and presented differentially on these pins. the outputs are open-collector, with 136 (typical) pull-up resistors tied to v rf + to aid impedance matching. if used single-ended, the unused output should be terminated to 50. see the applications information section for more details on impedance matching. v rf + (pin 13): 3.15 v to 3.45 v positive supply pin for rf circuitry. this pin should be bypassed directly to the ground plane using a 0.01 f ceramic capacitor as close to the pin as possible. bb (pin 14): rf reference bypass. this output has a 2.5k resistance and must be bypassed with a 1 f ceramic ca- pacitor to gnd. do not couple this pin to any other signal. vco C , vco + (pins 15, 16): vco input signals. the dif- ferential signal placed on these pins is buffered with a low noise amplifier and fed to the internal output and feedback dividers. these self-biased inputs must be ac-coupled and present a single-ended 121 ( typical) resistance to aid impedance matching. they may be used single- ended by bypassing vco C to gnd with a capacitor. see the applications information section for more details on impedance matching. v vco + (pin 23): 3.15 v to 3.45 v positive supply pin for vco circuitry. this pin should be bypassed directly to the ground plane using a 0.01 f ceramic capacitor as close to the pin as possible. gnd (24): negative power supply ( ground). this pin is attached directly to the die attach paddle ( dap) and should be tied directly to the ground plane. v cp + ( pin 25): 3.15 v to 5.25 v positive supply pin for charge pump circuitry. this pin should be bypassed directly to the ground plane using a 0.1 f ceramic capacitor as close to the pin as possible. cp ( pin 26): charge pump output. this bidirectional current output is normally connected to the external loop filter. see the applications information section for more details. v ref + (pin 27): 3.15 v to 3.45 v positive supply pin for reference input cir cuitry. this pin should be bypassed directly to the ground plane using a 0.1 f ceramic capaci- tor as close to the pin as possible.
ltc 6947 10 6947f for more information www.linear.com/ltc6947 b lock diagra m rf ? 1 7 2 11 gnd exposed pad 10 mute 9 29 rf + 12 v rf + 13 28 ref + ldo ldo regulator 425mhz 100mhz 1 to 31 1 to 6, 50% 1.7v to 2.6v 32 to 1023 mute ref ? 27 v ref + r_div lock pfd o_div n_div ? 350mhz to 6ghz 350mhz to 6ghz cp v vco + gnd gnd gnd gnd gnd 1ma to 11.2ma 26 23 21 gnd 22 20 19 18 17 25 v cp + v co + v co ? 24 gnd 6947 bd 14 bb serial port stat cs 6 sdo sdi sclk 8 v d + 5 4 3 + ? 16 15
ltc 6947 11 6947f for more information www.linear.com/ltc6947 o pera t ion the ltc6947 is a high performance fractional-n pll, and, combined with an external high performance vco, can produce low noise lo signals up to 6 ghz. the output frequency range may be further extended by utilizing the output divider. the device is able to achieve superior inte- grated phase noise by the combination of its extremely low in-band phase noise performance and the wide bandwidth allowed by its low spurious products. the fractional-n feedback divider uses an advanced ? modulator, resulting in virtually no discrete modulator spurious tones. the modulator may be disabled if integer -n feedback is required. r eference i nput b uffer the plls reference frequency is applied differentially on pins ref + and ref C . these high impedance inputs are self-biased and must be ac-coupled with 1 f capacitors (see figure 1 for a simplified schematic). alternatively, the inputs may be used single-ended by applying the refer- ence frequency at ref + and bypassing ref C to gnd with a 1 f capacitor. if the single-ended signal is greater than 2.7v p-p , then use a 47pf capacitor for the gnd bypass. a high quality signal must be applied to the ref inputs additional options are available through serial port register h0b to further refine the application. bits filt[1:0] control the reference input buffers lowpass filter, and should be set based upon f ref to limit the references wideband noise. the filt[1:0] bits must be set correctly to reach the l norm normalized in-band phase noise floor. see table 1 for recommended settings. table 1. filt[1:0] programming filt[1:0] f ref 3 <20mhz 2 na 1 20mhz to 50mhz 0 >50mhz the bst bit should be set based upon the input signal level to prevent the reference input buffer from saturating. see table 2 for recommended settings and the applications information section for programming examples. table 2. bst programming bst v ref 1 <2v p-p 0 2v p-p r eference (r) d ivider a 5- bit divider, r_div, is used to reduce the frequency seen at the pfd. its divide ratio r may be set to any inte- ger from 1 to 31, inclusive. use the rd[4:0] bits found in registers h06 to directly program the r divide ratio. see the applications information section for the relationship between r and the f ref , f pfd , f vco , and f rf frequencies. p hase /f re q uency d etector (pfd) the phase/frequency detector ( pfd), in conjunction with the charge pump, produces source and sink current pulses proportional to the phase difference between the outputs of the r and n dividers. this action provides the necessary feedback to phase-lock the loop, forcing a phase align- ment at the pfds inputs. the pfd may be disabled with the cprst bit which prevents up and down pulses from being produced. see figure 2 for a simplified schematic of the pfd. figure 1. simplified ref interface schematic 4.2k ref + ref ? 4.2k 6947 f01 1.9v bst bias v ref + v ref + lowpass filt[1:0] 1 28 as they provide the frequency reference to the entire pll. to achieve the parts in-band phase noise performance, apply a cw signal of at least 6 dbm into 50, or a square wave of at least 0.5v p-p with slew rate of at least 40v/s.
ltc 6947 12 6947f for more information www.linear.com/ltc6947 o pera t ion figure 2. simplified pfd schematic l ock i ndicator the lock indicator uses internal signals from the pfd to measure phase coincidence between the r and n divider output signals. it is enabled by programming lkct[1:0] in the serial port register h0c ( see table 5), and produces both lock and unlock status flags, available through both the stat output and serial port register h00. the user sets the phase difference lock window time t lww for a valid lock condition with the lkwin[2:0] bits. when using the device as a fractional-n synthesizer (fractional mode), the ? modulator changes the instantaneous phase seen at the pfd on every r_div and n_div cycle. the maximum allowable time difference in this case depends upon both the vco frequency f vco and also the charge pump linearization enable bit cple ( see the charge pump linearizer section for an explanation of this function). table 3 contains recommended settings for lkwin[2:0] when using the device in fractional mode. see the applications information section for examples. table 3. lkwin[2:0] fractional mode programming lkwin[2:0] t lww f vco (cple = 1) f vco (cple = 0) 0 5.0ns 2.97ghz 1.35ghz 1 7.35ns 2.00ghz 919mhz 2 10.7ns 1.39ghz 632mhz 3 15.8ns 941mhz 428mhz 4 23.0ns 646mhz 294mhz 5 34.5ns 431mhz 196mhz 6 50.5ns 294mhz 134mhz 7 76.0ns 196mhz 89mhz d q rst n div d q rst cprst up down 6947 f02 delay r div when using the device as an integer -n synthesizer (integer mode), the phase difference seen at the pfd is minimized by the feedback of the pll and no longer depends upon f vco . table 4 contains recommended settings for different f pfd frequencies when used in integer mode. table 4. lkwin[2:0] integer mode programming lkwin[2:0] t lww f pfd 0 5.0ns >6.8mhz 1 7.35ns 6.8mhz 2 10.7ns 4.7mhz 3 15.8ns 3.2mhz 4 23.0ns 2.2mhz 5 34.5ns 1.5mhz 6 50.5ns 1.0mhz 7 76.0ns 660khz the pfd phase difference must be less than t lww for the counts number of successive counts before the lock indicator asserts the lock flag. the lkct[1:0] bits found in register h0c are used to set counts depending upon the application. set lkct [1:0] = 0 to disable the lock in- dicator. see table 5 for lkct[1:0] programming and the applications information section for examples. table 5. lkct[1:0] programming lkct[1:0] counts 0 lock indicator disabled 1 32 2 256 3 2048 when the pfd phase difference is greater than t lww , the lock indicator immediately asserts the unlock status flag and clears the lock flag, indicating an out-of-lock condition. the unlock flag is immediately de-asserted when the phase difference is less than t lww . see figure ?3 below for more details. note that f ref must be present for the lock and unlock flags to properly assert and clear. c harge p ump the charge pump, controlled by the pfd, forces sink (down) or source ( up) current pulses onto the cp pin,
ltc 6947 13 6947f for more information www.linear.com/ltc6947 o pera t ion figure 4. simplified charge pump schematic figure 3. unlock and lock timing +t lww ?t lww unlock flag lock flag t = counts/f pfd 6947 f03 0 phase difference at pfd 26 + ? + ? cp i cp thi 0.9v v cp + v cp + tlo + ? 0.9v 6947 f04 + ? v cp + /2 cp linearizer control enable cpmid cpup up i lin cpdn cp[2:0] cpinv down nd[9:0] intn cple v cp + which should be connected to an appropriate loop filter. see figure 4 for a simplified schematic of the charge pump. the output current magnitude i cp may be set from 1 ma to 11.2ma using the cp[2:0] bits found in serial port register h0c. a larger i cp can result in lower in-band noise due to the lower impedance of the loop filter components, although currents larger than 5.6 ma typically cause worse spurious performance. see table 6 for programming specifics and the applications information section for loop filter examples. table 6. cp[2:0] programming cp[2:0] i cp 0 1.0ma 1 1.4ma 2 2.0ma 3 2.8ma 4 4.0ma 5 5.6ma 6 8.0ma 7 11.2ma the cpinv bit found in register h0d should be set for ap- plications requiring signal inversion from the pfd, such as for external loops using an op amp. a passive loop filter as shown in figure 14 requires cpinv = 0. an active loop filter as shown in figure 15 requires cpinv = 1 for a positive k vco . charge pump functions the charge pump contains additional features to aid in system startup. see table 7 for a summary. table 7. charge pump function bit descriptions bit description cpchi enable high voltage output clamp cpclo enable low voltage output clamp cpdn force sink current cpinv invert pfd phase cple linearizer enable cpmid enable mid-voltage bias cprst reset pfd cpup force source current cpwide extend current pulse width thi high voltage clamp flag tlo low voltage clamp flag the cpchi and cpclo bits found in register h0d enable the high and low voltage clamps, respectively. when cpchi is enabled and the cp pin voltage exceeds approximately v cp + C 0.9v , the thi status flag is set, and the charge pump sourcing current is disabled. alternately, when cpclo is enabled and the cp pin voltage is less than approximately 0.9v , the tlo status flag is set, and the charge pump sinking current is disabled. see figure ?4 for a simplified schematic.
ltc 6947 14 6947f for more information www.linear.com/ltc6947 o pera t ion the cpmid bit also found in register h0d enables a resis- tive v cp + /2 output bias which may be used to pre-bias troublesome loop filters into a valid voltage range. when using cpmid, it is recommended to also assert the cprst bit, forcing a pfd reset. both cpmid and cprst must be set to 0 for normal operation. the cpup and cpdn bits force a constant i cp source or sink current, respectively, on the cp pin. the cprst bit may also be used in conjunction with the cpup and cpdn bits, allowing a pre-charge of the loop to a known state, if required. cpup, cpdn, and cprst must be set to 0 to allow the loop to lock. the cpwide bit extends the charge pump output current pulse width by increasing the pfd reset paths delay value (see figure 2). cpwide is normally set to 0. charge pump linearizer when the ltc6947 is operated in fractional mode, the charge pumps current output versus its phase stimulus (its gain linearity) must be extremely accurate. the cp gain linearizer automatically adds a correction current i lin to minimize the charge pumps impact on in-band phase noise and spurious products during fractional operation. the cp gain linearizer is enabled by setting cple = 1. it is automatically disabled when in integer mode. cple should be set to 0 if cprst or cpmid are asserted to prevent the linearizer from producing unintended currents. vco i nput b uffer the vco frequency is applied differentially on pins vco + and vco C . the inputs are self-biased and must be ac-coupled. alternatively, the inputs may be used single-ended by ap- plying the vco frequency at vco + and bypassing vco C to gnd with a capacitor. each input provides a single-ended 121 resistance to aid in impedance matching at high frequencies. see the applications information section for matching guidelines. the bb pin is used to bias internal vco buffer circuitry. the bb pin has a 2 k output resistance and should be bypassed with a 1 f ceramic capacitor to gnd, giving a time constant of 2 ms. stable bias voltages are achieved after approximately 3 time constants following power-up. vco (n) d ivider the 10- bit n divider provides the feedback from the vco to the pfd. its divide ratio n is restricted to any integer from 35 to 1019, inclusive, when in fractional mode. the divide ratio may be programmed from 32 to 1023, inclusive, when in integer mode. use the nd[9:0] bits found in registers h06 and h07 to directly program the n divide ratio. see the applications information section for the relationship between n and the f ref , f pfd , f vco , and f rf frequencies. ? m odula tor the ? modulator changes the n dividers ratio each pfd cycle to achieve an average fractional divide ratio. the fractional numerator num[17:0] is programmable from 1 to 262143, or 2 18 C 1. the fractional denominator is fixed at 262144 (or 2 18 ), with the resulting fractional ratio f given by equation 3. see the applications information section for the relationship between num, f, and the f ref , f pfd , f vco , and f rf frequencies. the ? modulator uses digital signal processing (dsp) techniques to achieve an average fractional divide ratio. the modulator is clocked at the f pfd rate. this process produces output modulation noise known as quantization noise with a highpass frequency response. the external lowpass loop filter is used to filter this quantization noise to a level beneath the phase noise of the vco. this prevents the noise from contributing to the overall phase noise of the system. the loop filter must be designed to adequately filter the quantization noise. the oversampling ratio osr is defined as the ratio of the ? modulator clock frequency f pfd to the loop bandwidth 16 15 121 vco + vc0 ? 121 6947 f05 0.9v v vco + v vco + v vco + + ? figure 5. simplified vco interface schematic
ltc 6947 15 6947f for more information www.linear.com/ltc6947 o pera t ion bw of the pll ( see equation 10). see the applications information section for guidelines concerning the osr and the loop filter. when the desired output frequency is such that the needed num value is 0, the ltc6947 should be operated in integer mode (intn = 1). in integer mode, the modulator is placed in standby, with all blocks still powered up, thus allowing it to resume fractional operation immediately. enable numerator dither mode (dithen = 1) to further reduce spurious produced by the modulator. dither has no measurable impact on in-band phase noise, and is enabled by default. see table 8 for a complete list of modulator bit descriptions. modulator reset to achieve consistent spurious performance, the modulator dsp circuitry should be re-initialized by setting rstfn ?=?1 whenever num[17:0] is changed. setting autorst = 1 causes the rstfn bit to be set automatically whenever any of serial port registers h05 through h0a are written. when autorst is enabled, there is no need for a sepa- rate register write to set the rstfn bit. see table 8 for a summary of the modulator bits. table 8. fractional modulator bit descriptions bit description autorst automatically reset modulator when registers h05 to h0a are written dithen enable fractional numerator dither intn integer mode; fractional modulator placed in standby rstfn reset modulator (auto clears) seed seed value for pseudorandom dither algorithm ldo r egulator the adjustable low dropout ( ldo) regulator supplies power to the ? modulator. the regulator requires a low esr ceramic capacitor (esr < 0.8) connected to the ldo pin (pin 7) for stability. the capacitor value may range from 0.047f to 1f. the ldo voltage is set using the ldov[1:0] bits, and should be chosen based upon the f pfd frequency to minimize power and spurious. the regulator is disabled by setting the ldoen bit to 0. when disabled by using either the ldoen or pdfn bits, the ldo pin is connected directly to v d + using a low impedance switch, and the regulator is powered down. see table 9 for programming details. table 9. ldov[1:0] and ldoen programming ldov[1:0] ldoen v(ldo) f pfd 0 1 1.7v 34.3mhz 1 1 2.0v 45.9mhz 2 1 2.3v 56.1mhz 3 1 2.6v 66.3mhz x 0 v d + 76.1mhz o utput (o) d ivider the 3- bit o divider can reduce the frequency from the vco to extend the output frequency range. its divide ratio o may be set to any integer from 1 to 6, inclusive, outputting a 50% duty cycle even with odd divide values. use the od[2:0] bits found in register h0b to directly program the o divide ratio. see the applications information section for the relationship between o and the f ref , f pfd , f vco , and f rf frequencies. rf o utput b uffer the low noise, differential output buffer produces a dif- ferential output power of C4.3 dbm to +4.5 dbm, settable with bits rfo[1:0] according to table 10. the outputs may be combined externally, or used individually. terminate any unused output with a 50 resistor to v rf + . table 10. rfo[1:0] programming rfo[1:0} p rf (differential) p rf (single-ended) 0 C4.3dbm C7.3dbm 1 C1.5dbm C4.5dbm 2 1.6dbm C1.4dbm 3 4.5dbm 1.5dbm each output is open-collector with 136 pull-up resistors to v rf + , easing impedance matching at high frequencies. see figure 6 for circuit details and the applications infor- mation section for matching guidelines. the buffer may be muted with either the omute bit, found in register h02, or by forcing the mute input low.
ltc 6947 16 6947f for more information www.linear.com/ltc6947 o pera t ion s erial p ort the spi - compatible serial port provides control and monitoring functionality. a configurable status output stat gives additional instant monitoring. communication sequence the serial bus is comprised of cs , sclk, sdi, and sdo. data transfers to the part are accomplished by the se- rial bus master device first taking cs low to enable the ltc6947s port. input data applied on sdi is clocked on the rising edge of sclk, with all transfers msb first . the communication burst is terminated by the serial bus master returning cs high. see figure 7 for details. data is read from the part during a communication burst using sdo. readback may be multidrop ( more than one ltc6947 connected in parallel on the serial bus), as sdo is three-stated ( hi-z) when cs = 1, or when data is not being read from the part. if the ltc 6947 is not used in a multidrop configuration, or if the serial port master is not capable of setting the sdo line level between read sequences, it is recommended to attach a high value resistor of greater than 200 k between sdo and gnd to ensure the line returns to a known level during hi-z states. see figure 8 for details. single byte t ransfers the serial port is arranged as a simple memory map, with status and control available in 15 byte-wide registers. all data bursts are comprised of at least two bytes. the seven most significant bits of the first byte are the register address, with an lsb of 1 indicating a read from the part, and lsb of 0 indicating a write to the part. the subsequent byte, or bytes, is data from/to the specified register address. see figure 9 for an example of a detailed write sequence, and figure 10 for a read sequence. figure 8. serial port read timing diagram figure 7. serial port write timing diagram master?cs master?sclk t css t cs t ch data data 6947 f07 t ckl t ckh t css t csh master?sdi master?cs master?sclk ltc6947?sdo hi-z hi-z 6947 f08 8th clock data data t do t do t do t do 12 11 6947 f06 v rf + v rf + rf + 136 136 rf ? mute omute rfo[1:0] 9 mute figure 6. simplified rf interface schematic
ltc 6947 17 6947f for more information www.linear.com/ltc6947 o pera t ion figure 11 shows an example of two write communication bursts. the first byte of the first burst sent from the serial bus master on sdi contains the destination register ad- dress ( addr0) and an lsb of 0 indicating a write. the next byte is the data intended for the register at address addr0. cs is then taken high to terminate the transfer. the first byte of the second burst contains the destination register address ( addr1) and an lsb indicating a write. the next byte on sdi is the data intended for the register at address addr1. cs is then taken high to terminate the transfer. multiple byte transfers more efficient data transfer of multiple bytes is accom- plished by using the ltc6947s register address auto- increment feature as shown in figure 12. the serial port master sends the destination register address in the first byte and its data in the second byte as before, but continues sending bytes destined for subsequent registers. byte 1s address is addr0+1, byte 2 s address is addr0+2, and so on. if the register address pointer attempts to increment past 14 (h0e), it is automatically reset to 0. an example of an auto-increment read from the part is shown in figure 13. the first byte of the burst sent from the serial bus master on sdi contains the destination reg- ister address ( addr0) and an lsb of 1 indicating a read. once the ltc6947 detects a read burst, it takes sdo out of the hi-z condition and sends data bytes sequentially, beginning with data from register addr0. the part ignores all other data on sdi until the end of the burst. multidrop configuration several ltc6947s may share the serial bus. in this mul- tidrop configuration, sclk, sdi, and sdo are common between all parts. the serial bus master must use a separate cs for each ltc6947 and ensure that only one device has cs asserted at any time. it is recommended to attach a high value resistor to sdo to ensure the line returns to a known level during hi-z states. serial port registers the memory map of the ltc6947 may be found in table 11, with detailed bit descriptions found in table 12. the figure 10. serial port read sequence figure 9. serial port write sequence a6 a5 a4 a3 a2 7-bit register address hi-z master?cs master?sclk master?sdi ltc6947?sd0 a1 a0 0 d7 d6 d5 d4 d3 d2 d1 d0 8 bits of data 0 = write 6947 f09 16 clocks a6 a5 a4 a3 a2 7-bit register address hi-z hi-z a1 a0 1 d7x d6 d5 d4 d3 d2 d1 d0 dx 8 bits of data 1 = read 6947 f10 master?cs master?sclk master?sdi ltc6947?sdo 16 clocks
ltc 6947 18 6947f for more information www.linear.com/ltc6947 o pera t ion figure 11. serial port single byte write figure 12. serial port auto-increment write figure 13. serial port auto-increment read addr0 + wr hi-z master?cs master?sdi ltc6947?sdo byte 0 addr1 + wr byte 1 6947 f11 addr0 + wr hi-z master?cs master?sdi ltc6947?sdo byte 0 byte 1 byte 2 6947 f12 addr0 + rd don?t care hi-z hi-z master?cs master?sdi ltc6947?sdo 6947 f13 byte 0 byte 1 byte 2 table 11. serial port register contents addr msb [6] [5] [4] [3] [2] [1] lsb r/w default h00 * * unlock * * lock thi tlo r h01 * * x[5] * * x[2] x[1] x[0] r/w h04 h02 pdall pdpll * pdout pdfn * omute por r/w h06 h03 * * * * * autorst dithen intn r/w h06 h04 * * * * cple ldoen ldov[1] ldov[0] r/w h07 h05 seed[7] seed[6] seed[5] seed[4] seed[3] seed[2] seed[1] seed[0] r/w h11 h06 rd[4] rd[3] rd[2] rd[1] rd[0] * nd[9] nd[8] r/w h08 h07 nd[7] nd[6] nd[5] nd[4] nd[3] nd[2] nd[1] nd[0] r/w hfa h08 * * num[17] num[16] num[15] num[14] num[13] num[12] r/w h3f h09 num[11] num[10] num[9] num[8] num[7] num[6] num[5] num[4] r/w hff h0a num[3] num[2] num[1] num[0] * * rstfn * r/w hf0 h0b bst filt[1] filt[0] rfo[1] rfo[0] od[2] od[1] od[0] r/w hf9 h0c lkwin[2] lkwin[1] lkwin[0] lkct[1] lkct[0] cp[2] cp[1] cp[0] r/w h4f h0d cpchi cpclo cpmid cpinv cpwide cprst cpup cpdn r/w he4 h0e rev[3] rev[2] rev[1] rev[0] part [3] part [2] part [1] part [0] r hxx? *unused ? varies depending on version
ltc 6947 19 6947f for more information www.linear.com/ltc6947 o pera t ion table 12. serial port register bit field summary bits description default autorst reset modulator whenever registers h05 to h0a are written 1 bst ref buffer boost current 1 cp[2:0] cp output current h7 cpchi enable hi-voltage cp output clamp 1 cpclo enable low-voltage cp output clamp 1 cpdn force cp pump down 0 cpinv invert cp phase 0 cple cp linearizer enable 0 cpmid cp bias to mid-rail 1 cprst cp tr i -state 1 cpup force cp pump up 0 cpwide extend cp pulse width 0 dithen enable fractional numerator dither 1 filt[1:0] ref input buffer filter h3 intn integer mode; fractional modulator placed in standby 0 ldoen ldo enable 1 ldov[1:0] ldo voltage h3 lkct[1:0] pll lock cycle count h1 lkwin[2:0] pll lock indicator window h2 lock pll lock indicator flag nd[9:0] n divider value (nd[9:0] 32) h0fa num[17:0] fractional numerator value h3fff od[2:0] output divider value (0 < od[2:0] < 7) h1 omute mutes rf output 1 part [3:0] part code h0 pdall full chip powerdown 0 pdfn powers down ldo and modulator clock 0 pdout powers down n_div, rf output buffer 0 pdpll powers down ref, r_div, pfd, cpump 0 por force power-on-reset 0 rd[4:0] r divider value (rd[4:0] > 0) h001 rev[3:0] rev code h1 rfo[1:0] rf output power h3 rstfn force modulator reset (auto clears) 0 seed[7:0] modulator dither seed value h11 thi cp clamp high flag tlo cp clamp low flag unlok pll unlock flag x[5,2:0] stat output or mask h04 register address shown in hexadecimal format under the addr column is used to specify each register. each register is denoted as either read-only ( r) or read-write (r/w). the registers default value on device power-up or after a reset is shown at the right. the read-only register at address h00 is used to determine different status flags. these flags may be instantly output on the stat pin by configuring register h01. see the stat output section for more information. the read-only register at address h0e is a rom byte for device identification. s tat output the stat output pin is configured with the x[5,2:0] bits of register h01. these bits are used to bit-wise mask, or enable, the corresponding status flags of status register h00, according to equation 1. the result of this bit-wise boolean operation is then output on the stat pin. stat = or (reg00[5,2:0] and reg 01[5,2:0]) (1) or, expanded, stat = (unlock and x[5]) or (lock and x[2]) or (thi and x[1]) or (tlo and x[0]) for example, if the application requires stat to go high whenever the lock or thi flags are set, then x[2] and x[1] should be set to 1, giving a register value of h06. block power-down control the ltc6947s power-down control bits are located in register h02, described in table 12. different portions of the device may be powered down independently. care must be taken with the lsb of the register, the por ( power-on- reset) bit. when written to a 1, this bit forces a full reset of the parts digital circuitry to its power-up default state.
ltc 6947 20 6947f for more information www.linear.com/ltc6947 a pplica t ions i n f or m a t ion i ntroduction a pll is a complex feedback system that may conceptually be considered a frequency multiplier. the system multiplies the frequency input at ref and outputs a higher frequency at rf . the pfd, charge pump, n divider, external vco, and loop filter form a feedback loop to accurately control the output frequency (see figure 14). the external loop filter is used to set the plls loop bandwidth bw. lower bandwidths generally have better spurious performance and lower ? modulator quantization noise. higher bandwidths can have better total integrated phase noise. the r and o divider and input frequency f ref are used to set the output frequency resolution. when in fractional mode, the ? modulator changes the n dividers ratio each pfd cycle to produce an average fractional divide ratio. this achieves a much smaller frequency resolution for a given f pfd as compared to integer mode. o utput f re q uency when the loop is locked, the frequency f vco ( in hz) produced at the output of the vco is determined by the reference frequency f ref , the r and n divider values, and the fractional value f, given by equation 2: f vco = f ref ? n + f ( ) r (2) where the fractional value f is given by equation 3: f = num 2 18 (3) num is programmable from 1 to 262143, or 2 18 C 1. when using the ltc6947 in integer mode, f = 0. the pfd frequency f pfd is given by the following equation: f pfd = f ref r (4) and f vco may be alternatively expressed as: f vco = f pfd ? (n + f) (5) the output frequency f rf produced at the output of the o divider is given by equation 6: f rf = f vco o (6) using the above equations, the minimum output frequency resolution f step(min) produced by a unit change in the fractional numerator num while in fractional mode is given by equation 7: f step(min) = f ref r ? o ? 2 18 (7) al ternatively, to calculate the numerator step size num step needed to produce a given frequency step f step(frac) , use equation 8: figure 14. pll loop diagram r_div n_div r o_div o (n + f) f pfd ltc6947 ref (f ref ) f vco k pfd k vco 26 rf (f rf ) cp r z c i c p c2 loop filter (fourth order) lf(s) 6947 f14 vco i cp ? r1 l1
ltc 6947 21 6947f for more information www.linear.com/ltc6947 a pplica t ions i n f or m a t ion num step = f step(frac) ? r ? o ? 2 18 f ref (8) the output frequency resolution f step(int) produced by a unit change in n while in integer mode is given by equa- tion 9: f step(int) = f ref r ? o (9) l oop f il ter d esign a stable pll system requires care in designing the external loop filter. the linear technology fracnwizard applica- tion, available from www.linear.com, aids in design and simulation of the complete system. the loop design should use the following algorithm: 1) determine the output frequency f rf and frequency step size f step based on application requirements. using equations 2, 4, 6, and 7, change f ref , n, r, and o until the application frequency constraints are met. use the minimum r value that still satisfies the constraints. 2) select the open loop bandwidth bw constrained by f pfd and oversampling ratio osr. the osr is the ratio of f pfd to bw (see equation 10): osr = f pfd bw or bw = f pfd osr (10) where bw and f pfd are in hz. a stable loop, both in integer and fractional mode, requires that the osr is greater than or equal to 10. further, in fractional mode, osr must be high enough to allow the loop filter to reduce modulator quantization noise to an acceptable level. choosing a higher-order loop filter when using the ? modulator allows for a smaller osr, and thus a larger loop bandwidth. linear technology s fracnwizard helps choose the appropriate osr and bw values. 3) select loop filter component r z and charge pump cur- rent i cp based on bw and the vco gain factor, k vco . bw ( in hz) is approximated by the following equation: bw ? i cp ? r z ? k vco 2 ? ? n or r z = 2 ? ? bw ? n i cp ? k vco (11) where k vco is in hz/v, i cp is in amps, and r z is in ohms. k vco is the vcos frequency tuning sensitivity, and may be determined from the vco specifications. use i cp = 5.6 ma to lower in-band noise unless component values force a lower setting. 4) select loop filter components c i and c p based on bw and r z . a reliable second-order loop filter design can be achieved by using the following equations for the loop capacitors (in farads). c i = 3.5 2 ? ? bw ? r z (12) c p = 1 7 ? ? bw ? r z (13) use fracnwizard to aid in the design of higher order loop filters. l oop f il ters u sing an o p a mp some vco tune voltage ranges are greater than the ltc6947 s charge pump voltage range. an active loop filter using an op amp can increase the tuning voltage range. to maintain the ltc6947s high performance, care must be given to picking an appropriate op amp. the op amp input common mode voltage should be biased within the ltc6947 charge pumps voltage range, while its output voltage should achieve the vco tuning range. see figure 15 for an example op amp loop filter.
ltc 6947 22 6947f for more information www.linear.com/ltc6947 the op amps input bias current is supplied by the charge pump; minimizing this current keeps spurs related to f pfd low. the input bias current should be less than the charge pump leakage ( found in the electrical characteristics sec- tion) to avoid increasing spurious products. op amp noise sources are highpass filtered by the pll loop filter and should be kept at a minimum, as their ef- fect raises the total system phase noise beginning near the loop bandwidth. choose a low noise op amp whose input-referred voltage noise is less than the thermal noise of r z . additionally, the gain-bandwidth of the op amp should be at least 20 times the loop bandwidth to limit phase margin degradation. the lt ? 1678 is an op amp that works very well in most applications. an additional r-c lowpass filter ( formed by r p2 and c p2 in figure 15) connected at the input of the vco will limit the op amp output noise sources. the bandwidth of this filter should be approximately 15 to 20 times the pll loop bandwidth to limit loop phase margin degradation. r p2 should be small ( preferably less than r z ) to minimize its noise impact on the loop. however, picking too small of a value can make the op amp unstable as it has to drive the capacitor in this filter. d esign and p rogramming e xample this programming example uses the dc1846 with the ltc6947. assume the following parameters of interest: f ref = 100mhz at 7dbm into 50 f step = 50khz f rf = 2415.15mhz f vco = 2328mhz to 2536mhz k vco = 78mhz/v l m(vco) = C127dbc/hz at 100khz offset determining divider values following the loop filter design algorithm, first determine all the divider values. the maximum f pfd while in fractional mode is less than 100 mhz, so r must be greater than 1. further, the minimum n value in fractional mode is 35, setting the lower limit on r: r = 2 then, using equations 4 and 6, calculate the following values: o =1 f pfd = 50mhz then using equation 5: n + f = 2415.15mhz 50mhz = 48.303 therefore: n = 48 f = 0.303 then, from equation 3, num = 0.303 ? 2 18 = 79430 selecting filter type and loop bandwidth the next step in the algorithm is choosing the open loop bandwidth. select the minimum bandwidth resulting from the below constraints. 1) the osr must be at least 10 (sets absolute maximum bw). a pplica t ions i n f or m a t ion figure 15. op amp loop filter c p lf(s) c i c p2 k vco 6947 f15 47f cp i cp vco (f vco ) v cp + /2 5k 5k v cp + ltc6947 r z r p2 ? + c2 loop filter (fourth order) r1 l1
ltc 6947 23 6947f for more information www.linear.com/ltc6947 a pplica t ions i n f or m a t ion 2) the integrated phase noise due to thermal noise should be minimized, neglecting any modulator noise. 3) however, the loop bandwidth must also be narrow enough to adequately filter the modulator s quantization noise. fracnwizard reports loop bandwidths resulting from each of the above constraints. the quantization noise constrained results vary according to the shape of the external loop filter. fracnwizard reports an optimal bandwidth for several filter types. fracnwizard reports the thermal noise optimized loop bandwidth is 31.6 khz. filter 2 ( third order response) has a quantization noise constrained bw of 56.2 khz, making it a good choice. select filter 2 and use the smaller of the two bandwidths (31.6 khz) for optimal integrated phase noise. use equation 10 to calculate osr: osr = 50mhz 31.6khz = 1582 loop filter component selection now set loop filter resistor r z and charge pump current i cp . using an i cp of 5.6 ma and the specified k vco of 78mhz/v, fracnwizard uses equation?11 to determine r z : r z = 2 ? ? 31.6k ? 48 5.6m ? 78m r z = 21.8 for the 3 rd order filter 2, fracnwizard uses modified equations 7 and 8 to calculate c i , c p : c i = 4 2 ? ? 31.6k ? 21.8 = 924nf c p = 1 10.5 ? ? 31.6k ? 21.8 = 44nf fracnwizard calculates r1 and c2 to be: r1 = 21.8 c2 = 29.3nf these values are used with the schematic of figure 15 (with l1 unused). status output programming this example will use the stat pin to indicate the ltc6947 is locked. program x [2] = 1 to force the stat pin high whenever the lock flag asserts: reg01 = h04 power register programming for correct pll operation all internal blocks should be enabled. omute may remain asserted ( or the mute pin held low) until programming is complete. for omute = 1: reg02 = h02 autorst programming set the modulator auto reset option (autorst = 1) and the ? modulator modes (dithen = 1, intn = 0) at the same time: reg03 = h06 the ? modulator will be reset at the end of the spi write communication burst ( assuming an auto-increment write is used to write all registers). ldo programming use table 9 and f pfd = 50 mhz to determine v(ldo) and ldov[1:0]: v(ldo) = 2.3v and ldov[1:0] = 1 use ldov[1:0] and ldoen = 1 ( to enable the ldo) to set reg04. cple should be set to 1 to reduce in-band noise and spurious due to the ? modulator: reg04 = h0e seed programming the seed[7:0] value is used to initialize the ? modulator dither circuitry. use the default value: reg 05 = h11 r and n divider and numerator programming program registers reg06 to reg0a with the previously determined r and n divider and numerator values. because
ltc 6947 24 6947f for more information www.linear.com/ltc6947 a pplica t ions i n f or m a t ion the autorst bit was previously set to 1, rstfn does not need to be set: reg06 = h10 reg07 = h30 reg08 = h13 reg09 = h64 reg0a = h60 reference input settings and output divider programming from table 1, filt = 0 for a 100 mhz reference frequency. next, convert 7 dbm into v p-p . for a cw tone, use the fol- lowing equation with r = 50: v p-p ? r ? 10 (dbm C 21)/20 (14) this gives v p-p = 1.41 v, and, according to table 2, set bst = 1. now program reg0b, assuming maximum rf output power ( rfo [1:0] = 3 according to table 10) and od [2:0] = 1: reg0b = h99 lock detect and charge pump current programming next, determine the lock indicator window from f pfd . from table 3 we see that lkwin[1:0] = 1 with a t lww of 7.35ns for cple = 1 and f vco = 2415 mhz. the ltc6947 will con- sider the loop locked as long as the phase coincidence at the pfd is within 132, as calculated below. phase = 360 ? t lww ? f pfd = 360 ? 7.35n ? 50m 132 choosing the correct counts value depends upon the osr. smaller ratios dictate larger counts values, although application requirements will vary. a counts value of 32 will work for the osr ratio of 1582. from table? 5, lkct[1:0]?=?1 for 32 counts. using table 6 with the previously selected i cp of 5.6ma gives cp [3:0] = 5. this gives enough information to pro- gram reg0c: reg0c = h2d charge pump function programming the dc1846 includes an lt1678i op amp in the loop filter. this allows the circuit to reach the voltage range speci- fied for the vcos tuning input. however, it also adds an inversion in the loop transfer function. compensate for this inversion by setting cpinv = 1. this example does not use the additional voltage clamp features to allow fault condition monitoring. the loop feedback provided by the op amp will force the charge pump output to be equal to the op amp positive input pins voltage. disable the charge pump voltage clamps by setting cpchi = 0 and cpclo = 0. disable all the other charge pump functions ( cpmid, cprst, cpup, and cpdn) to allow the loop to lock: reg0d = h10 the loop should now lock. now un-mute the output by setting omute = 0 (assumes the mute pin is high). reg02 = h00 r eference s ource c onsidera tions a high quality signal must be applied to the ref inputs as they provide the frequency reference to the entire pll. as mentioned previously, to achieve the parts in-band phase noise performance, apply a cw signal of at least 6dbm into 50, or a square wave of at least 0.5v p-p with slew rate of at least 40v/s. the ltc6947 may be driven single-ended to cmos levels (greater than 2.7v p-p ). apply the reference signal at ref + , and bypass ref C to gnd with a 47 pf capacitor. the bst bit must also be set to 0, according to guidelines given in table 2. the ltc6947 achieves an integer mode in- band normalized phase noise floor l norm(int) = C226 dbc/hz typical, and a fractional mode phase noise floor l norm(frac) = C225 dbc/hz typical. to calculate its equivalent input phase noise floor l in , use the following equation 15. l in = l norm + 10 ? log 10 (f ref ) (15) for example, using a 10 mhz reference frequency in integer mode gives an input phase noise floor of C156dbc/hz. the reference frequency sources phase noise must be at
ltc 6947 25 6947f for more information www.linear.com/ltc6947 a pplica t ions i n f or m a t ion least 3 db better than this to prevent limiting the overall system performance. i n -b and o utput p hase n oise the in-band phase noise floor l out produced at f rf may be calculated by using equation 16. l out = l norm + 10 ? log 10 (f pfd ) (16) + 20 ? log 10 (f rf /f pfd ) or l out l norm + 10 ? log 10 (f pfd ) + 20 ? log 10 (n/o) where l norm is C226 dbc / hz for integer mode and C225dbc/hz for fractional mode. as can be seen, for a given pfd frequency f pfd , the output in-band phase noise increases at a 20 db-per-decade rate with the n divider count. so, for a given output frequency f rf , f pfd should be as large as possible ( or n should be as small as possible) while still satisfying the applications frequency step size requirements. o utput p hase n oise d ue to 1/f n oise in-band phase noise at very low offset frequencies may be influenced by the ltc6947s 1/ f noise, depending upon f pfd . use the normalized in-band 1/ f noise l 1/f of C274dbc/ hz with equation 17 to approximate the output 1/ f phase noise at a given frequency offset f offset . l out(1/f) (f offset ) = l 1/f + 20 ? log 10 (f rf ) (17) C 10 ? log 10 (f offset ) unlike the in-band noise floor l out , the 1/ f noise l out(1/f) does not change with f pfd , and is not constant over offset frequency. see figure 16 for an example of integer mode in-band phase noise for f pfd equal to 3 mhz and 100mhz. the total phase noise will be the summation of l out and l out(1/f) . vco i nput m a tching the vco inputs may be used differentially or single - ended . each input provides a single-ended 121 resistance to aid in impedance matching at high frequencies. the inputs are self-biased and must be ac-coupled using 100 pf capaci- tors (or 270pf for vco frequencies less than 500mhz). the inputs may be used single-ended by applying the ac- coupled vco frequency at vco + and bypassing vco C to gnd with a 100 pf capacitor (270 pf for frequencies less than 500 mhz). measured vco + s-parameters ( with vco C bypassed with 100 pf to gnd) are shown in table 13 to aid in the design of external impedance matching networks. table 13. single-ended vco + input impedance fre q uency (mhz) impedance () s11 (db) 250 118 C j78 C5.06 500 83.6 C j68.3 C5.90 1000 52.8 C j56.1 C6.38 1500 35.2 C j41.7 C6.63 2000 25.7 C j30.2 C6.35 2500 19.7 C j20.6 C5.94 3000 17.6 C j11.2 C6.00 3500 17.8 C j3.92 C6.41 4000 19.8 + j4.74 C7.20 4500 21.5 + j15.0 C7.12 5000 21.1 + j19.4 C6.52 5500 27.1 + j22.9 C7.91 6000 38.3 + j33.7 C8.47 6500 36.7 + j42.2 C6.76 7000 46.2 + j40.9 C8.11 7500 76.5 + j36.8 C9.25 8000 84.1+ j52.2 C7.27 offset frequency (hz) 10 phase noise (dbc/hz) ?110 ?100 100k 6947 f16 ?120 ?130 100 1k 10k ?90 total noise f pfd = 3mhz total noise f pfd = 100mhz 1/f noise contribution figure 16. theoretical integer mode in-band phase noise, f rf = 2500mhz
ltc 6947 26 6947f for more information www.linear.com/ltc6947 ib spur level (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 6947 f17 frequency offset from 3.256ghz (hz) 1k 10k 10m 1m 100k f vco 3.256ghz f pfd = 61.44mhz loop bw = 15khz cple = 1 o = 1 n = 53 swept num note 13 i nteger b oundary s purs integer boundary spurs are caused by intermodulation between harmonics of the pfd frequency f pfd and the vco frequency f vco . the coupling between the frequency source harmonics can occur either on- or off-chip. the spurs are located at offset frequencies defined by the beat frequency between the reference harmonics and the vco frequency, and are attenuated by the loop filter. the spurs only occur while in fractional mode. integer boundary spurs are most commonly seen when the fractional value f approaches either zero or one such that the vco frequency offset from an integer frequency is within the loop bandwidth: f pfd ? f bw or f pfd ? (1 C f) bw the spur will have a relatively constant power in-band, and is attenuated by the loop out-of-band. an example integer boundary spur measurement is shown in figure 17. rf o utput m a tching the rf outputs may be used in either single-ended or dif- ferential configurations. using both rf outputs differentially will result in approximately 3 db more output power than single-ended. impedance matching to an external load in both cases requires external chokes tied to v rf + . measured rf s-parameters are shown below in table?14 to aid in the design of impedance matching networks. table 14. single-ended rf output impedance fre q uency (mhz) impedance () s11 (db) 100 133.0 C j16.8 C6.7 500 110.8 C j46.1 C6.8 1000 74.9 C j57.0 C6.9 1500 49.0 C j51.3 C6.7 2000 34.4 C j41.4 C6.5 2500 27.0 C j32.1 C6.5 3000 23.2 C j24.1 C6.6 3500 21.6 C j15.9 C7.1 4000 20.9 C j7.7 C7.5 4500 20.1 C j0.2 C7.4 5000 18.1 + j7.4 C6.4 5500 16.7 + j12.5 C5.6 6000 17.1 + j16.1 C5.5 6500 20.2 + j20.1 C6.2 7000 26.9 + j24.6 C7.6 7500 38.8 + j32.3 C8.8 8000 52.9 + j43.1 C8.2 single-ended impedance matching is accomplished using the circuit of figure 18, with component values found in table 15. using smaller inductances than recommended can cause phase noise degradation, especially at lower center frequencies. a pplica t ions i n f or m a t ion figure 18. single-ended output matching schematic rf +(?) l c c s 50 to 50 load v rf + rf ?(+) l c c s 6947 f18 v rf + figure 17. integer boundary spur power vs frequency offset from boundary
ltc 6947 27 6947f for more information www.linear.com/ltc6947 a pplica t ions i n f or m a t ion table 15. suggested single-ended matching component values f rf (mhz) l c (nh) c s (pf) 350 to 1500 180 270 1000 to 6000 68 100 return loss measured on the dc1846 using the above component values is shown in figure 19. a broadband match is achieved using an {l c , c s } of either {68nh, 100pf} or {180nh, 270 pf}. however, for maximum output power and best phase noise performance, use the recommended component values of table 15. l c should be a wirewound inductor selected for maximum q factor and srf, such as the coilcraft hp series of chip inductors. v rf + voltage. figure 20 shows a surface mount baluns connections with a dc feed pin. table 16. suggested baluns f rf (mhz) part number manufacturer type 350 to 900 #617db-1673 toko tl 400 to 600 hhm1589b1 tdk smt 600 to 1400 bd0810j50200 anaren smt 600 to 3000 mabact0065 m/a-com tl 1000 to 2000 hhm1518a3 tdk smt 1400 to 2000 hhm1541e1 tdk smt 1900 to 2300 2450bl15b100e johanson smt 2000 to 2700 hhm1526 tdk smt 3700 to 5100 hhm1583b1 tdk smt 4000 to 6000 hhm1570b1 tdk smt figure 20. example smt balun connection figure 21. example tl balun connection ltc6947 v rf + rf ? rf + to 50 load 6947 f20 12 balun 2 3 1 5 4 6 11 balun pin configuration 1 2 3 4 5 6 unbalanced port gnd or dc feed balanced port balanced port gnd nc ltc6947 v rf + rf ? rf + to 50 load pri sec 6947 f21 12 11 figure 19. rf single-ended return loss 0 1 2 3 4 5 6 7 frequency (ghz) s11 (db) ?6 ?4 ?2 6947 f19 ?10 ?16 0 ?8 ?12 ?14 68nh, 100pf 180nh, 270pf the ltc6947s differential rf outputs may be combined using an external balun to drive a single-ended load. the advantages are approximately 3 db more output power than each output individually and better 2 nd order harmonic performance. for lower frequencies, transmission line ( tl) baluns such as the m/a-com mabact0065 and the toko #617 db-1673 provide good results. at higher frequencies, surface mount (smt) baluns such as those produced by tdk, anaren, and johanson technology, can be attractive alternatives. see table 16 for recommended balun part numbers versus frequency range. the listed smt baluns contain internal chokes to bias rf and also provide input-to-output dc isolation. the pin denoted as gnd or dc feed should be connected to the the listed tl baluns do not provide input-to-output dc isolation and must be ac-coupled at the output. figure 21 displays rf connections using these baluns.
ltc 6947 28 6947f for more information www.linear.com/ltc6947 s upply b ypassing and pcb l ayout g uidelines care must be taken when creating a pcb layout to mini- mize power supply decoupling and ground inductances. all power supply v + pins should be bypassed directly to the ground plane using a 0.1 f ceramic capacitor as close to the pin as possible. multiple vias to the ground plane should be used for all ground connections, including to the power supply decoupling capacitors. the packages exposed pad is a ground connection, and must be soldered directly to the pcb land pattern. the pcb land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance ( see figure 22 for an example). see qfn package users guide, page 8, on linear technology websites packaging information page for specific recom- mendations concerning land patterns and land via solder masks. a link is provided below. http://www.linear.com/designtools/packaging a pplica t ions i n f or m a t ion r eference s ignal r outing , s purious , and p hase n oise the charge pump operates at the pfds comparison frequency f pfd . the resultant output spurious energy is small and is further reduced by the loop filter before it modulates the vco frequency. however, improper pcb layout can degrade the ltc6947 s inherent spurious performance. care must be taken to prevent the reference signal f ref from coupling onto the vcos tune line, or into other loop filter signals. example suggestions are the following. 1) do not share power supply decoupling capacitors between same-voltage power supply pins. 2) use separate ground vias for each power supply decou- pling capacitor, especially those connected to v ref + , v d + , ldo, v cp + , and v vco + . 3) physically separate the reference frequency signal from the loop filter and vco. figure 22. example exposed pad land pattern 6947 f22
ltc 6947 29 6947f for more information www.linear.com/ltc6947 output frequency (mhz) 3220 (dbc) ?30 ?35 ?40 ?45 ?50 3270 3320 3370 6947 ta02b 3420 baseband = 100khz at 500mv pk lo leakage ratio unadjusted image rejection typical a pplica t ions modulator lo for low image rejection and low noise floor measured image rejection and lo leakage ratio vs output frequency measured noise floor at 70mhz offset vs rf output power 47f 0.1f r = 1, f pfd = 61.44mhz n = 52.6 to 55.5 lbw = 14.5khz o = 1 6.8nf 0.01f 1f 0.01f 3.3v 3.3v 0.01f 68nh 68nh 4.99k 0.01f 5v 3.3v 68.1 unused output available for other use avago vmmk-2503 vtune 5v 8v 100pf 100pf 22nf 6.8nf 3.3v ltc6947iufd stat vco ? cs mute sdi v d + ldo rf + rf ? gnd sclk vco + gnd v rf + ref + bb sdo gnd gnd gnd gnd gnd v vco + gnd v cp + cp v ref + ref ? gnd 75 0.1f 6.8nf 4.99k 100pf 0.1f 0.1f 0.1f 22nf 470nf 100pf 220nf 61.44mhz spi bus 51.1 1f 3.3v 1f rfmd umx-918-d16-g 0.1f 18v 3.3v 4.7f 50 mini-circuits lfcn-3800+ lpf 68.1 50 1 47nf 1nf 6.8pf 1nf 5v 3.3v ? + lt1678is8 out 68h ltc5588-1 baseband i-channel baseband q-channel en gnd lop lom gnd nc linopt gnd bbmq bbpq gnd gndrf gnd gndrf v cc1 gnd bbmi bbpi gnd gndrf v cc2 gndrf gndrf nc nc rf 100nf 6947 ta02a f lo = 3230mhz to 3410mhz in 234.4hz steps rf output, 3230mhz to 3410mhz carrier p lo = 13dbm, ~ ltc 6947 30 6947f for more information www.linear.com/ltc6947 6.8nf 75 6.8nf 22nf 470nf 220nf 68.1 47nf 47f 0.1f 0.01f 1f 0.01f 3.3v 3.3v 0.01f 68nh 68nh 4.99k 0.01f 5v 3.3v vtune 5v 8v 100pf 100pf 22nf 3.3v ltc6947iufd stat vco ? cs mute sdi v d + ldo rf + rf ? gnd sclk vco + gnd v rf + ref + bb sdo gnd gnd gnd gnd gnd v vco + gnd v cp + cp v ref + ref ? gnd 0.1f 4.99k 100pf 0.1f 0.1f 0.1f 100pf 315.5mhz, 15dbm 51.1 1f 3.3v 1f rfmd umx-918-d16-g 0.1f 18v 3.3v ? + lt1678is8 out 6947 ta03a spi bus unused output available for other use crystek ccso-914x 315.5mhz data- converter clock 50 f lo = 3230mhz to 3410mhz o = 1 6.8nf 16.5 16.5 16.5 this application example illustrates a straightforward programming method to minimize integer boundary spurs. switch the reference divider value, r, between two predetermined values to avoid fractional values, f, close to 0 or 1. f ref = 315.5mhz for r1 = 6: f pfd (r1) = 52.58mhz, f step (r1) = 200.59hz for r2 = 5: f pfd (r2) = 63.10mhz, f step (r2) = 240.7hz first, calculate f spur (r), frequency offset of the integer-boundary spur nearest integer boundary as a distance from the carrier, for each r value. next, let r = r1 for f spur (r1) > f spur (r2), else let r = r2 f spur (r) = f ? f ref r , for f < 0.5 f spur (r) = (1 ? f) ? f ref r , for f 0.5 where f = num 2 18 68.1 68h lo frequency (mhz) 3220 note: spurs up to ?70dbc can be found near f values of 0.5 in very narrow bands (10s of khz) and up to ?75dbc near f values of 0.333 or 0.667. appropriately switching between r1 and r2 can avoid these spurs. spur level (dbc) ?95 ?100 ?105 ?110 ?115 3270 3320 3370 6947 ta03b 3420 r1 = 6 r2 = 5 typical a pplica t ions integer boundary spur avoidance integer boundary spur avoidance results (measured at nearest integer boundary)
ltc 6947 31 6947f for more information www.linear.com/ltc6947 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b)
ltc 6947 32 6947f for more information www.linear.com/ltc6947 ? linear technology corporation 2014 lt 0814 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc6947 r ela t e d p ar t s typical a pplica t ions part number description comments ltc6946-x ultralow noise and spurious integer-n synthesizer with integrated vco 370mhz to 6.4ghz, C226dbc/hz normalized in-band phase noise floor, C157dbc/hz wideband output phase noise floor ltc6945 ultralow noise and spurious integer-n synthesizer 350mhz to 6ghz, C226dbc/hz normalized in-band phase noise floor, C157dbc/hz wideband output phase noise floor ltc6948-x ultralow noise fractional-n synthesizer with integrated vco 370mhz to 6.4ghz, C226dbc/hz normalized in-band phase noise floor, C157dbc/hz wideband output phase noise floor ltc6957 low phase noise, dual output buffer/driver/logic converter optimized conversion of sine waves to logic levels, lvpecl/lvds/cmos outputs, dc-300mhz, 45fsrms additive jitter (lvpecl) ltc5588-1 ultrahigh oip3 i/q modulator 200mhz to 6ghz, 31dbm oip3, C160.6dbm/hz noise floor modulator lo for low image rejection and low noise floor 47f 0.1f r = 1, f pfd = 61.44mhz n = 52.6 to 55.5 lbw = 14.5khz o = 1 6.8nf 0.01f 1f 0.01f 3.3v 3.3v 0.01f 68nh 68nh 4.99k 0.01f 5v 3.3v 68.1 unused output available for other use avago vmmk-2503 vtune 5v 8v 100pf 100pf 22nf 6.8nf 3.3v ltc6947iufd stat vco ? cs mute sdi v d + ldo rf + rf ? gnd sclk vco + gnd v rf + ref + bb sdo gnd gnd gnd gnd gnd v vco + gnd v cp + cp v ref + ref ? gnd 75 0.1f 6.8nf 4.99k 100pf 0.1f 0.1f 0.1f 22nf 470nf 100pf 220nf 61.44mhz spi bus 51.1 1f 3.3v 1f rfmd umx-918-d16-g 0.1f 18v 3.3v 4.7f 50 mini-circuits lfcn-3800+ lpf 68.1 50 1 47nf 1nf 6.8pf 1nf 5v 3.3v ? + lt1678is8 out 68h ltc5588-1 baseband i-channel baseband q-channel en gnd lop lom gnd nc linopt gnd bbmq bbpq gnd gndrf gnd gndrf v cc1 gnd bbmi bbpi gnd gndrf v cc2 gndrf gndrf nc nc rf 100nf 6947 ta04 f lo = 3230mhz to 3410mhz in 234.4hz steps rf output, 3230mhz to 3410mhz carrier p lo = 13dbm, ~

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